UVM SoC Testbench

Name: Maven Silicon
Brand: Maven Silicon
Rating: 4.7 (1481 reviews)

bySivakumar P R
May 15, 2020
1 minute read
7786 Views

This video explains how we reuse the IP level UVM test benches at the SoC [System on Chip] level, reusing the IP level UVM sequences to generate various SoC level test scenarios.

To learn SystemVerilog in detail, please explore our online verification course at https://elearn.maven-silicon.com/vlsi-verification-systemverilog-uvm

Sivakumar P R
Sivakumar P R is the Founder and CEO of Maven Silicon. He is responsible for the company's vision, business, and technology. Sivakumar is a seasoned engineering professional who has worked in various fields, including electrical engineering, academia, and semiconductors for more than 25 years. Before founding Maven Silicon, he worked in the top EDA companies Synopsys, Cadence and Siemens EDA as a verification consultant.