Soft IP is a synthesizable RTL in the form of gate level netlist which is tied to a specific technology node. Hard IP is a routed netlist GDSII which is tied to a specific technology. But Chiplet is a physically realised and tested IP in the form of silicon on a specific technology node, like a small chip.
Usually we create the monolithic System on Chips connecting 100s of soft or hard IPs and then fabricate them as chips on a particular technology node. The entire chip is fabricated on a particular technology node like 22nm, 14nm or 10nm etc. These SoCs will be scaled up in terms of features with more number of IPs by moving to the next technology node. By reducing the transistor size through advanced technology nodes, we would be able to add more IPs as we can pack more transistors into the same chip. This kind of monolithic SoC scale up is an expensive fabrication process at higher technology nodes like 10nm, 7nm etc.
As the monolithic SoC scale up is expensive, can we create the SoCs by directly connection the chips/IPs which have already been created at different technology nodes? Yes, it’s possible with the Chiplet approach.
With a chiplet model, those 100 IP blocks are hardened into smaller dies or chiplets. In theory, you would have a large catalog of chiplets from various IC vendors. Then, you can mix-and-match them to build a system. Chiplets could be made at different process nodes and re-used in different designs.
There are several approaches to chiplets. The basic idea is that you have a menu of modular chips, or chiplets, in a library. Then, you assemble chiplets in a package and connect them using a die-to-die interconnect scheme. In theory, the chiplet approach is a fast and less expensive way to assemble various types of third-party chips, such as I/Os, memory and processor cores, in a package.
Reference:
https://community.cadence.com/cadence_blogs_8/b/spi/posts/chiplets
https://semiengineering.com/the-chiplet-race-begins/
