You should be good at writing the source code for RTL and testbench in Verilog HDL to learn SystemVerilog. Not only the syntax, you should also be familiar with all the Verilog language concepts like concurrency, abstraction levels, data-flow-level modelling, synthesis coding style, blocking and non-blocking assignments, inertial and intra assignment delays, etc.
SystemVerilog – called as SV is the superset of Verilog and you can consider it as a latest version of Verilog. You can use SV for both design and verification. As we can do RTL coding comfortably with Verilog itself, we prefer SV mainly for RTL verification. SV supports OOP, randomisation, functional coverage, interfaces, mailbox, semaphores, assertions, etc. which are not available in Verilog for verification. As a fresher you can learn the basic concepts from the online forums like Verification Academy https://verificationacademy.com, but to learn the testbench implementation and verification process you can take up the online courses or any other hands-on courses provided by the industry experts. I have recently published an online verification course https://elearn.maven-silicon.com/vlsi-verification-systemverilog-uvm considering young VLSI aspirants like you.
Our VLSI Industry expects you to know how to use all the language features to create the reusable class-based verification environment and run the regression simulation, as a hands-on engineer. Most of the best textbooks available in the market explain the concepts and language features well but they don’t focus on right TB architecture, verification planning, complete environment implementation, etc. So, you can think of referring good textbooks and LRMs while working on the project, during coding phase.
