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Technical Lead

Shanthi heads front-end verification training for academic engagements and corporate internships. Her articles reverberate her extensive experience in the semiconductor industry and add value to our VLSI aspirants' careers.

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Verification

What is UVM Factory?

The factory is a centralized location to create the instance of the uvm component and object classes in UVM....
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Verification

SystemVerilog Event Scheduler

The SystemVerilog language is defined in terms of a discrete event execution model. A SystemVerilog description consists of connected threads of execution or processes. Proces...
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Verification

Clock Domain Crossing

Today’s device needs multiple clocks with increasing system integration, peripherals & external interfaces, and power management. In a design with multiple clocks, clock dom...
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