VLSI Training
Verification
UVM SoC Testbench
This video explains how we reuse the IP level UVM test benches at the SoC [System on Chip] level, reusing the IP level UVM sequences to generate various SoC level test scenari...
Verification
How can we model a transaction for the Scoreboard?
We define the transaction mainly based on the DUT [Design Under Test - RTL design] interface for the complete testbench infrastructure[Verification Environment], irrespective ...
Digital Electronics
SOP Vs POS
Many of you aspiring electronics engineers might be wondering ‘Why do we prefer SOP over POS when it comes to designing a digital circuit?’....
Verification
How do you verify your DUT thoroughly?
It’s not simple as you always assume and misguide others saying, ‘all you need is a great coding skill to write a testbench in SystemVerilog or UVM and the verification jo...
Verification
ASIC Verification Trends
The industry uses majorly three kinds of verification technologies: Dynamic Verification – Simulation based verification...
Verification
SystemVerilog Testbench/Verification Environment Architecture
Most of the well-known SystemVerilog textbooks available in the market explain the language concepts focusing more on language constructs, keywords, datatypes, examples, etc.,...
Verification
Functional Coverage
In this article, let us see how functional coverage is different from code coverage and how do we use it to sign-off the design verification....
Verilog HDL
What are the coding skills required for an analog circuit and layout design engineer?
Analog circuit design still happens at the layout level. The layout engineer places and connects all the analog components and creates the layout using EDA tools....
VLSI Industry
Semiconductor Industry
Global semiconductor industry’s yearly revenue in 2018 was $476.7 Billion. Semiconductor industry includes different kinds of companies like Chip Makers – ASIC & FPGA, Fab...
Verification
SystemVerilog Interfaces
This video explains why we prefer SystemVerilog interfaces than Verilog port level connections to build the IPs & Chips. It also explains the difference between Verilog port l...
Verification
Test Plan Vs Verification Plan[Vplan]
Test Plan is a traditional term primarily used for the directed test cases that we used to create in HDL - Verilog/VHDL. But in SystemVerilog [SV], we create random test cases...
Verification
Why do we prefer Packets/Transactions to create SV TB as a TLM?
In SystemVerilog, you can define the transaction[packet/frame] using class data type. But you should know why we prefer transactions to implement SV TB as a TLM[Transaction Le...
VLSI Industry
Are there good opportunities for the freshers in the VLSI Industry?
The Semiconductor/VLSI Industry in India is growing huge, no doubt. Almost all the top semiconductor and EDA corporations have operations in India....
Verification
How do I learn SystemVerilog in a week?
You can learn and get some exposure, but becoming an expert user of SystemVerilog[SV] depends on your prior programming experience in Verilog and any OOP based languages like ...
Newsletters
Newsletter – Apr 2020
"There's no abiding success without commitment." - Tony Robbins. The last quarter was very busy for us at Maven Silicon!...
SoC Design
System-on-Chip – SoC
Why SoC? We need System-on-Chip [SoC] to realize highly portable devices that give more performance and consume less power. Laptop is one of the best examples....
Verification
Is it worth reading SystemVerilog LRM?
Language Reference Manual is the main source of reference for everyone, EDA vendor, Design & Verification Engineer, Training vendors, etc....
Verification
Which protocols are good for a fresh VLSI verification engineer to get a job?
Mostly we use AMBA bus protocols AXI/AHB for the on-chip bus [backplane] communication in any SoC. So, learning AMBA protocols will be a huge advantage....
Verification
PSS – Portable Test and Stimulus Standard
Every aspiring and growing verification engineer might be searching for the answer to the question ‘What is PSS?’, as it’s an interesting concept that will transform the...
Verification
