The industry uses majorly three kinds of verification technologies:
- Dynamic Verification – Simulation based verification
- Static Verification – Formal verification
- Emulation & FPGA prototyping – Hardware based verification
Dynamic Verification: This simulation-based verification technology demands testbenches in HVL like SystemVerilog to verify the IP/Sub-System level RTL designs. Constrained-random, Assertions, Code and Functional Coverage are the most popular techniques/methodologies which are based on dynamic verification technology.
Static Verification: This static verification technology demands user defined/ automated formal properties [assertions] to verify the module/IP level RTL designs. Examples of automatic formal application tools include: SoC integration connectivity checking, deadlock detection, X semantic safety checks, coverage reachability analysis, and many other properties that can be automatically extracted and then formally proven.
Emulation and FPGA prototyping: This hardware-based verification technology demands the user to synthesize and map the design & TB components on the configurable chip [FPGAs]. Emulation and FPGA prototyping are primarily used to verify complex chips & SoCs, running simulation at higher speeds, 5-10X greater than simulation.
Simulation-based techniques are unable to keep up with today’s growing complexity of the Chips and SoCs. This is particularly true when simulating large SoCs that include both software and embedded processor core models.
The emulation and FPGA prototyping have become key platforms for SoC integration verification where both hardware and software are integrated into a system for the first time. In addition to SoC verification, emulation and FPGA prototyping are also used today as a platform for software development.
